OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 281

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7787d 07h /ethmac/trunk/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 7788d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 7796d 03h /ethmac/trunk/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 7852d 06h /ethmac/trunk/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 7857d 05h /ethmac/trunk/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7857d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7858d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7860d 02h /ethmac/trunk/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7860d 05h /ethmac/trunk/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7865d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7892d 06h /ethmac/trunk/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7892d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7901d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7920d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 7922d 05h /ethmac/trunk/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 7924d 05h /ethmac/trunk/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 7924d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 7927d 03h /ethmac/trunk/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 7927d 04h /ethmac/trunk/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 7927d 04h /ethmac/trunk/bench/verilog/tb_ethernet.v
177 Bug in MIIM fixed. mohor 7927d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
170 Headers changed. mohor 7927d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7927d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
158 Typo fixed. mohor 7932d 06h /ethmac/trunk/bench/verilog/tb_ethernet.v
156 Valid testbench. mohor 7934d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7979d 06h /ethmac/trunk/bench/verilog/tb_ethernet.v
117 Clock mrx_clk set to 2.5 MHz. mohor 7983d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 7983d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.