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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 346

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Rev Log message Author Age Path
346 Updated project location olof 4087d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
345 Temporarily disable failing tests olof 4087d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
344 bit 9 in phy control register is self clearing olof 4093d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
343 Address miss should not be asserted on short frames olof 4097d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
342 Added cast to avoid inequality when comparing different data types olof 4097d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
338 root 4891d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
335 New directory structure. root 4948d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
334 Minor fixes for Icarus simulator. igorm 6396d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
331 Tests for delayed CRC and defer indication added. igorm 6425d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
318 Latest Ethernet IP core testbench. tadejm 6757d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 6869d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 6918d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 6976d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7177d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 7178d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 7186d 06h /ethmac/trunk/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 7242d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 7247d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7247d 23h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7248d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v

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