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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 348

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Rev Log message Author Age Path
348 Added option to dump VCD files olof 3357d 08h /ethmac/trunk/bench/verilog/tb_ethernet.v
346 Updated project location olof 3357d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
345 Temporarily disable failing tests olof 3357d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
344 bit 9 in phy control register is self clearing olof 3363d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
343 Address miss should not be asserted on short frames olof 3367d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
342 Added cast to avoid inequality when comparing different data types olof 3367d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
338 root 4161d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
335 New directory structure. root 4218d 18h /ethmac/trunk/bench/verilog/tb_ethernet.v
334 Minor fixes for Icarus simulator. igorm 5666d 20h /ethmac/trunk/bench/verilog/tb_ethernet.v
331 Tests for delayed CRC and defer indication added. igorm 5695d 15h /ethmac/trunk/bench/verilog/tb_ethernet.v
318 Latest Ethernet IP core testbench. tadejm 6027d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 6139d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 6188d 21h /ethmac/trunk/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 6246d 16h /ethmac/trunk/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 6447d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 6448d 15h /ethmac/trunk/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 6456d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 6512d 12h /ethmac/trunk/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 6517d 11h /ethmac/trunk/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 6518d 02h /ethmac/trunk/bench/verilog/tb_ethernet.v

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