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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 356

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263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7250d 01h /ethmac/trunk/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7250d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7252d 07h /ethmac/trunk/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7252d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7257d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7284d 10h /ethmac/trunk/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7284d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7293d 14h /ethmac/trunk/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7312d 13h /ethmac/trunk/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 7314d 09h /ethmac/trunk/bench/verilog/tb_ethernet.v

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