URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 364

Rev	Log message	Author	Age	Path
266	Flow control test almost finished.	mohor	7825d 22h	/ethmac/trunk/bench/verilog/tb_ethernet.v
263	test_mac_full_duplex_flow_control tests pretty much finished. TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) finished. TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps ) finished.	mohor	7826d 13h	/ethmac/trunk/bench/verilog/tb_ethernet.v
260	test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame finished.	mohor	7827d 02h	/ethmac/trunk/bench/verilog/tb_ethernet.v
254	Temp version.	mohor	7828d 19h	/ethmac/trunk/bench/verilog/tb_ethernet.v
252	Just some updates.	tadejm	7828d 22h	/ethmac/trunk/bench/verilog/tb_ethernet.v
243	Late collision is not reported any more.	tadejm	7834d 02h	/ethmac/trunk/bench/verilog/tb_ethernet.v
227	Changed BIST scan signals.	tadejm	7860d 23h	/ethmac/trunk/bench/verilog/tb_ethernet.v
223	Some code changed due to bug fixes.	tadejm	7861d 02h	/ethmac/trunk/bench/verilog/tb_ethernet.v
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	7870d 02h	/ethmac/trunk/bench/verilog/tb_ethernet.v
194	Full duplex tests modified and testbench bug repaired.	tadej	7889d 01h	/ethmac/trunk/bench/verilog/tb_ethernet.v