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URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] - Rev 368

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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 3837d 12h /ethmac/trunk/rtl/
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 3900d 10h /ethmac/trunk/rtl/
366 Readded eth_top.v with a deprecation warning olof 4024d 14h /ethmac/trunk/rtl/
365 Whitespace cleanup olof 4025d 13h /ethmac/trunk/rtl/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4026d 10h /ethmac/trunk/rtl/
360 Added partial implementation of the debug register from ORPSoC olof 4027d 18h /ethmac/trunk/rtl/
359 Verilator linting fixes olof 4029d 20h /ethmac/trunk/rtl/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4031d 10h /ethmac/trunk/rtl/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4031d 10h /ethmac/trunk/rtl/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4031d 12h /ethmac/trunk/rtl/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4031d 13h /ethmac/trunk/rtl/
354 Whitespace cleanup olof 4031d 13h /ethmac/trunk/rtl/
353 Inherit fixes for bit width of constants from ORPSoC olof 4033d 15h /ethmac/trunk/rtl/
352 Removed delayed assignments from rtl code olof 4037d 21h /ethmac/trunk/rtl/
351 Turn defines into parameters in eth_cop olof 4046d 11h /ethmac/trunk/rtl/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4046d 11h /ethmac/trunk/rtl/
349 Make all parameters configurable from top level olof 4047d 12h /ethmac/trunk/rtl/
346 Updated project location olof 4048d 14h /ethmac/trunk/rtl/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4058d 14h /ethmac/trunk/rtl/
338 root 4852d 16h /ethmac/trunk/rtl/

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