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[/] [ethmac/] [trunk/] [rtl/] - Rev 138

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Rev Log message Author Age Path
110 m_wb_cyc_o signal released after every single transfer. mohor 7963d 05h /ethmac/trunk/rtl/
109 Comment removed. mohor 7963d 06h /ethmac/trunk/rtl/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8030d 16h /ethmac/trunk/rtl/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8039d 17h /ethmac/trunk/rtl/
104 FCS should not be included in NibbleMinFl. mohor 8041d 11h /ethmac/trunk/rtl/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 8041d 12h /ethmac/trunk/rtl/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8041d 12h /ethmac/trunk/rtl/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8041d 12h /ethmac/trunk/rtl/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 8041d 12h /ethmac/trunk/rtl/
97 Small typo fixed. lampret 8065d 10h /ethmac/trunk/rtl/

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