OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] - Rev 242

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7820d 19h /ethmac/trunk/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7820d 19h /ethmac/trunk/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7820d 19h /ethmac/trunk/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7820d 19h /ethmac/trunk/rtl/
238 Defines fixed to use generic RAM by default. mohor 7832d 23h /ethmac/trunk/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7835d 04h /ethmac/trunk/rtl/
232 fpga define added. mohor 7840d 22h /ethmac/trunk/rtl/
229 case changed to casex. mohor 7846d 20h /ethmac/trunk/rtl/
227 Changed BIST scan signals. tadejm 7847d 00h /ethmac/trunk/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7847d 02h /ethmac/trunk/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7851d 01h /ethmac/trunk/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7854d 02h /ethmac/trunk/rtl/
218 Typo error fixed. (When using Bist) mohor 7854d 04h /ethmac/trunk/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7855d 01h /ethmac/trunk/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7855d 01h /ethmac/trunk/rtl/
212 Minor $display change. mohor 7855d 01h /ethmac/trunk/rtl/
211 Bist added. mohor 7855d 01h /ethmac/trunk/rtl/
210 BIST added. mohor 7855d 01h /ethmac/trunk/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7871d 23h /ethmac/trunk/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7871d 23h /ethmac/trunk/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.