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[/] [ethmac/] [trunk/] [rtl/] - Rev 272

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Rev Log message Author Age Path
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7233d 10h /ethmac/trunk/rtl/
232 fpga define added. mohor 7239d 04h /ethmac/trunk/rtl/
229 case changed to casex. mohor 7245d 02h /ethmac/trunk/rtl/
227 Changed BIST scan signals. tadejm 7245d 06h /ethmac/trunk/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7245d 07h /ethmac/trunk/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7249d 07h /ethmac/trunk/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7252d 07h /ethmac/trunk/rtl/
218 Typo error fixed. (When using Bist) mohor 7252d 09h /ethmac/trunk/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7253d 06h /ethmac/trunk/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7253d 06h /ethmac/trunk/rtl/

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