OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] - Rev 355

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
355 Import Julius Baxter's verilator hints from ORPSoC olof 4656d 07h /ethmac/trunk/rtl/
354 Whitespace cleanup olof 4656d 08h /ethmac/trunk/rtl/
353 Inherit fixes for bit width of constants from ORPSoC olof 4658d 09h /ethmac/trunk/rtl/
352 Removed delayed assignments from rtl code olof 4662d 15h /ethmac/trunk/rtl/
351 Turn defines into parameters in eth_cop olof 4671d 05h /ethmac/trunk/rtl/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4671d 05h /ethmac/trunk/rtl/
349 Make all parameters configurable from top level olof 4672d 06h /ethmac/trunk/rtl/
346 Updated project location olof 4673d 08h /ethmac/trunk/rtl/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4683d 08h /ethmac/trunk/rtl/
338 root 5477d 10h /ethmac/trunk/rtl/
335 New directory structure. root 5534d 15h /ethmac/trunk/rtl/
333 Some small fixes + some troubles fixed. igorm 6983d 05h /ethmac/trunk/rtl/
332 Case statement improved for synthesys. igorm 6996d 11h /ethmac/trunk/rtl/
330 Warning fixes. igorm 7011d 13h /ethmac/trunk/rtl/
329 Defer indication fixed. igorm 7011d 14h /ethmac/trunk/rtl/
328 Delayed CRC fixed. igorm 7011d 14h /ethmac/trunk/rtl/
327 Defer indication fixed. igorm 7011d 14h /ethmac/trunk/rtl/
326 Delayed CRC fixed. igorm 7011d 14h /ethmac/trunk/rtl/
325 Defer indication fixed. igorm 7011d 15h /ethmac/trunk/rtl/
323 Accidently deleted line put back. igorm 7308d 15h /ethmac/trunk/rtl/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7312d 10h /ethmac/trunk/rtl/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7312d 14h /ethmac/trunk/rtl/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7352d 16h /ethmac/trunk/rtl/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7455d 13h /ethmac/trunk/rtl/
306 Lapsus fixed (!we -> ~we). simons 7456d 10h /ethmac/trunk/rtl/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7478d 07h /ethmac/trunk/rtl/
302 mbist signals updated according to newest convention markom 7504d 18h /ethmac/trunk/rtl/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7515d 10h /ethmac/trunk/rtl/
297 Artisan ram instance added. simons 7568d 09h /ethmac/trunk/rtl/
288 This file was not part of the RTL before, but it should be here. simons 7604d 11h /ethmac/trunk/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.