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[/] [ethmac/] [trunk/] [rtl/] - Rev 365

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Rev Log message Author Age Path
365 Whitespace cleanup olof 4689d 20h /ethmac/trunk/rtl/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4690d 17h /ethmac/trunk/rtl/
360 Added partial implementation of the debug register from ORPSoC olof 4692d 01h /ethmac/trunk/rtl/
359 Verilator linting fixes olof 4694d 03h /ethmac/trunk/rtl/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4695d 17h /ethmac/trunk/rtl/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4695d 17h /ethmac/trunk/rtl/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4695d 19h /ethmac/trunk/rtl/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4695d 20h /ethmac/trunk/rtl/
354 Whitespace cleanup olof 4695d 20h /ethmac/trunk/rtl/
353 Inherit fixes for bit width of constants from ORPSoC olof 4697d 22h /ethmac/trunk/rtl/
352 Removed delayed assignments from rtl code olof 4702d 04h /ethmac/trunk/rtl/
351 Turn defines into parameters in eth_cop olof 4710d 17h /ethmac/trunk/rtl/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4710d 18h /ethmac/trunk/rtl/
349 Make all parameters configurable from top level olof 4711d 19h /ethmac/trunk/rtl/
346 Updated project location olof 4712d 20h /ethmac/trunk/rtl/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4722d 20h /ethmac/trunk/rtl/
338 root 5516d 23h /ethmac/trunk/rtl/
335 New directory structure. root 5574d 04h /ethmac/trunk/rtl/
333 Some small fixes + some troubles fixed. igorm 7022d 18h /ethmac/trunk/rtl/
332 Case statement improved for synthesys. igorm 7035d 23h /ethmac/trunk/rtl/

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