URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] - Rev 55

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
55	Changed that were lost with last update put back to the file.	mohor	8109d 21h	/ethmac/trunk/rtl/
54	Addition of new module eth_addrcheck.v	billditt	8110d 11h	/ethmac/trunk/rtl/
53	Addition of new module eth_addrcheck.v	billditt	8110d 11h	/ethmac/trunk/rtl/
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8110d 12h	/ethmac/trunk/rtl/
50	checks destination address for Unicast, Multicast and Broadcast ops	billditt	8110d 13h	/ethmac/trunk/rtl/
48	RxOverRun added to statuses.	mohor	8112d 15h	/ethmac/trunk/rtl/
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8112d 15h	/ethmac/trunk/rtl/
46	HASH0 and HASH1 registers added.	mohor	8112d 15h	/ethmac/trunk/rtl/
43	Tx status is written back to the BD.	mohor	8113d 23h	/ethmac/trunk/rtl/
42	Rx status is written back to the BD.	mohor	8116d 16h	/ethmac/trunk/rtl/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8118d 18h	/ethmac/trunk/rtl/
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8119d 15h	/ethmac/trunk/rtl/
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8123d 19h	/ethmac/trunk/rtl/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8132d 21h	/ethmac/trunk/rtl/
37	Link in the header changed.	mohor	8132d 22h	/ethmac/trunk/rtl/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8181d 17h	/ethmac/trunk/rtl/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8181d 21h	/ethmac/trunk/rtl/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8181d 22h	/ethmac/trunk/rtl/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8203d 18h	/ethmac/trunk/rtl/
24	Log file added.	mohor	8228d 21h	/ethmac/trunk/rtl/
23	Number of addresses (wb_adr_i) minimized.	mohor	8228d 21h	/ethmac/trunk/rtl/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8228d 23h	/ethmac/trunk/rtl/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8229d 20h	/ethmac/trunk/rtl/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8253d 17h	/ethmac/trunk/rtl/
18	Few little NCSIM warnings fixed.	mohor	8266d 18h	/ethmac/trunk/rtl/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8293d 18h	/ethmac/trunk/rtl/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8301d 00h	/ethmac/trunk/rtl/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8302d 17h	/ethmac/trunk/rtl/
14	Unconnected signals are now connected.	mohor	8306d 23h	/ethmac/trunk/rtl/
10	Directory structure changed. Files checked and joind together.	mohor	8309d 11h	/ethmac/trunk/rtl/

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] - Rev 55

Filtering Options