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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 368


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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 4513d 20h /ethmac/trunk/rtl/verilog
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 4576d 18h /ethmac/trunk/rtl/verilog
366 Readded eth_top.v with a deprecation warning olof 4700d 22h /ethmac/trunk/rtl/verilog
365 Whitespace cleanup olof 4701d 21h /ethmac/trunk/rtl/verilog
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4702d 18h /ethmac/trunk/rtl/verilog
360 Added partial implementation of the debug register from ORPSoC olof 4704d 02h /ethmac/trunk/rtl/verilog
359 Verilator linting fixes olof 4706d 04h /ethmac/trunk/rtl/verilog
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4707d 18h /ethmac/trunk/rtl/verilog
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4707d 18h /ethmac/trunk/rtl/verilog
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4707d 20h /ethmac/trunk/rtl/verilog
355 Import Julius Baxter's verilator hints from ORPSoC olof 4707d 21h /ethmac/trunk/rtl/verilog
354 Whitespace cleanup olof 4707d 21h /ethmac/trunk/rtl/verilog
353 Inherit fixes for bit width of constants from ORPSoC olof 4709d 23h /ethmac/trunk/rtl/verilog
352 Removed delayed assignments from rtl code olof 4714d 05h /ethmac/trunk/rtl/verilog
351 Turn defines into parameters in eth_cop olof 4722d 19h /ethmac/trunk/rtl/verilog
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4722d 19h /ethmac/trunk/rtl/verilog
349 Make all parameters configurable from top level olof 4723d 20h /ethmac/trunk/rtl/verilog
346 Updated project location olof 4724d 22h /ethmac/trunk/rtl/verilog
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4734d 22h /ethmac/trunk/rtl/verilog
338 root 5529d 00h /ethmac/trunk/rtl/verilog

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