URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 110

Rev	Log message	Author	Age	Path
85	Log info was missing.	mohor	8090d 05h	/ethmac/trunk/rtl/verilog/
84	LinkFail signal was not latching appropriate bit.	mohor	8090d 05h	/ethmac/trunk/rtl/verilog/
83	MAC address recognition was not correct (bytes swaped).	mohor	8090d 05h	/ethmac/trunk/rtl/verilog/
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8090d 07h	/ethmac/trunk/rtl/verilog/
80	Small fixes for external/internal DMA missmatches.	mohor	8094d 09h	/ethmac/trunk/rtl/verilog/
79	RetryCntLatched was unused and removed from design	mohor	8094d 10h	/ethmac/trunk/rtl/verilog/
78	WB_SEL_I was unused and removed from design	mohor	8094d 10h	/ethmac/trunk/rtl/verilog/
77	Interrupts changed	mohor	8094d 10h	/ethmac/trunk/rtl/verilog/
76	Interrupts changed in the top file	mohor	8094d 10h	/ethmac/trunk/rtl/verilog/
75	r_Bro is used for accepting/denying frames	mohor	8094d 10h	/ethmac/trunk/rtl/verilog/