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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 127

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Rev Log message Author Age Path
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7969d 14h /ethmac/trunk/rtl/verilog/
126 InvalidSymbol generation changed. mohor 7969d 14h /ethmac/trunk/rtl/verilog/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7969d 14h /ethmac/trunk/rtl/verilog/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7971d 16h /ethmac/trunk/rtl/verilog/
120 Unused files removed. mohor 7971d 17h /ethmac/trunk/rtl/verilog/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7971d 17h /ethmac/trunk/rtl/verilog/
118 ShiftEnded synchronization changed. mohor 7975d 08h /ethmac/trunk/rtl/verilog/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7976d 16h /ethmac/trunk/rtl/verilog/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7977d 14h /ethmac/trunk/rtl/verilog/
113 RxPointer bug fixed. mohor 7984d 05h /ethmac/trunk/rtl/verilog/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7984d 19h /ethmac/trunk/rtl/verilog/
111 Master state machine had a bug when switching from master write to
master read.
mohor 7985d 08h /ethmac/trunk/rtl/verilog/
110 m_wb_cyc_o signal released after every single transfer. mohor 7985d 12h /ethmac/trunk/rtl/verilog/
109 Comment removed. mohor 7985d 12h /ethmac/trunk/rtl/verilog/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8052d 22h /ethmac/trunk/rtl/verilog/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8062d 00h /ethmac/trunk/rtl/verilog/
104 FCS should not be included in NibbleMinFl. mohor 8063d 17h /ethmac/trunk/rtl/verilog/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 8063d 18h /ethmac/trunk/rtl/verilog/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8063d 18h /ethmac/trunk/rtl/verilog/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8063d 19h /ethmac/trunk/rtl/verilog/

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