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Rev Log message Author Age Path
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7757d 02h /ethmac/trunk/rtl/verilog/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7758d 02h /ethmac/trunk/rtl/verilog/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7759d 03h /ethmac/trunk/rtl/verilog/
165 HASH improvement needed. mohor 7759d 06h /ethmac/trunk/rtl/verilog/
164 Ethernet debug registers removed. mohor 7759d 06h /ethmac/trunk/rtl/verilog/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7760d 04h /ethmac/trunk/rtl/verilog/
160 error acknowledge cycle termination added to display. mohor 7760d 04h /ethmac/trunk/rtl/verilog/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7761d 00h /ethmac/trunk/rtl/verilog/
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 7764d 22h /ethmac/trunk/rtl/verilog/
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
mohor 7764d 22h /ethmac/trunk/rtl/verilog/
148 Bug when last byte of destination address was not checked fixed. mohor 7764d 22h /ethmac/trunk/rtl/verilog/
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 7764d 22h /ethmac/trunk/rtl/verilog/
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7764d 22h /ethmac/trunk/rtl/verilog/
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7764d 22h /ethmac/trunk/rtl/verilog/
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 7781d 01h /ethmac/trunk/rtl/verilog/
141 Syntax error fixed. mohor 7783d 18h /ethmac/trunk/rtl/verilog/
140 Syntax error fixed. mohor 7783d 18h /ethmac/trunk/rtl/verilog/
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7783d 18h /ethmac/trunk/rtl/verilog/
138 Synchronous reset added. mohor 7783d 19h /ethmac/trunk/rtl/verilog/
137 Defines for register width added. mii_rst signal in MIIMODER register
mohor 7783d 19h /ethmac/trunk/rtl/verilog/

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