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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 17

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Rev Log message Author Age Path
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 7710d 03h /ethmac/trunk/rtl/verilog/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 7717d 08h /ethmac/trunk/rtl/verilog/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7719d 02h /ethmac/trunk/rtl/verilog/
14 Unconnected signals are now connected. mohor 7723d 07h /ethmac/trunk/rtl/verilog/
10 Directory structure changed. Files checked and joind together. mohor 7725d 19h /ethmac/trunk/rtl/verilog/

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