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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 238

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Rev	Log message	Author	Age	Path
238	Defines fixed to use generic RAM by default.	mohor	7855d 16h	/ethmac/trunk/rtl/verilog
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7857d 21h	/ethmac/trunk/rtl/verilog
232	fpga define added.	mohor	7863d 16h	/ethmac/trunk/rtl/verilog
229	case changed to casex.	mohor	7869d 14h	/ethmac/trunk/rtl/verilog
227	Changed BIST scan signals.	tadejm	7869d 17h	/ethmac/trunk/rtl/verilog
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7869d 19h	/ethmac/trunk/rtl/verilog
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7873d 18h	/ethmac/trunk/rtl/verilog
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7876d 19h	/ethmac/trunk/rtl/verilog
218	Typo error fixed. (When using Bist)	mohor	7876d 21h	/ethmac/trunk/rtl/verilog
214	Signals for WISHBONE B3 compliant interface added.	mohor	7877d 18h	/ethmac/trunk/rtl/verilog
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7877d 18h	/ethmac/trunk/rtl/verilog
212	Minor $display change.	mohor	7877d 18h	/ethmac/trunk/rtl/verilog
211	Bist added.	mohor	7877d 18h	/ethmac/trunk/rtl/verilog
210	BIST added.	mohor	7877d 18h	/ethmac/trunk/rtl/verilog
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7894d 16h	/ethmac/trunk/rtl/verilog
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7894d 16h	/ethmac/trunk/rtl/verilog
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7897d 17h	/ethmac/trunk/rtl/verilog
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7905d 20h	/ethmac/trunk/rtl/verilog
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7906d 20h	/ethmac/trunk/rtl/verilog
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7907d 21h	/ethmac/trunk/rtl/verilog

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 238

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