URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 239

Rev	Log message	Author	Age	Path
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7904d 15h	/ethmac/trunk/rtl/verilog
165	HASH improvement needed.	mohor	7904d 18h	/ethmac/trunk/rtl/verilog
164	Ethernet debug registers removed.	mohor	7904d 18h	/ethmac/trunk/rtl/verilog
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7905d 16h	/ethmac/trunk/rtl/verilog
160	error acknowledge cycle termination added to display.	mohor	7905d 16h	/ethmac/trunk/rtl/verilog
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	7906d 12h	/ethmac/trunk/rtl/verilog
150	Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal was not used OK.	mohor	7910d 10h	/ethmac/trunk/rtl/verilog
149	Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 connected.	mohor	7910d 10h	/ethmac/trunk/rtl/verilog
148	Bug when last byte of destination address was not checked fixed.	mohor	7910d 10h	/ethmac/trunk/rtl/verilog
147	ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to the control frames connected.	mohor	7910d 10h	/ethmac/trunk/rtl/verilog