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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 250

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Rev	Log message	Author	Age	Path
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7975d 01h	/ethmac/trunk/rtl/verilog/
248	wb_rst_i is used for MIIM reset.	mohor	7976d 01h	/ethmac/trunk/rtl/verilog/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7979d 04h	/ethmac/trunk/rtl/verilog/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7980d 00h	/ethmac/trunk/rtl/verilog/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7980d 20h	/ethmac/trunk/rtl/verilog/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7980d 20h	/ethmac/trunk/rtl/verilog/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7980d 20h	/ethmac/trunk/rtl/verilog/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7980d 20h	/ethmac/trunk/rtl/verilog/
238	Defines fixed to use generic RAM by default.	mohor	7993d 00h	/ethmac/trunk/rtl/verilog/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7995d 05h	/ethmac/trunk/rtl/verilog/
232	fpga define added.	mohor	8000d 23h	/ethmac/trunk/rtl/verilog/
229	case changed to casex.	mohor	8006d 21h	/ethmac/trunk/rtl/verilog/
227	Changed BIST scan signals.	tadejm	8007d 01h	/ethmac/trunk/rtl/verilog/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	8007d 03h	/ethmac/trunk/rtl/verilog/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	8011d 02h	/ethmac/trunk/rtl/verilog/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	8014d 03h	/ethmac/trunk/rtl/verilog/
218	Typo error fixed. (When using Bist)	mohor	8014d 05h	/ethmac/trunk/rtl/verilog/
214	Signals for WISHBONE B3 compliant interface added.	mohor	8015d 02h	/ethmac/trunk/rtl/verilog/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	8015d 02h	/ethmac/trunk/rtl/verilog/
212	Minor $display change.	mohor	8015d 02h	/ethmac/trunk/rtl/verilog/
211	Bist added.	mohor	8015d 02h	/ethmac/trunk/rtl/verilog/
210	BIST added.	mohor	8015d 02h	/ethmac/trunk/rtl/verilog/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	8032d 00h	/ethmac/trunk/rtl/verilog/
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	8032d 00h	/ethmac/trunk/rtl/verilog/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	8035d 01h	/ethmac/trunk/rtl/verilog/
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	8043d 04h	/ethmac/trunk/rtl/verilog/
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	8044d 04h	/ethmac/trunk/rtl/verilog/
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	8045d 05h	/ethmac/trunk/rtl/verilog/
165	HASH improvement needed.	mohor	8045d 08h	/ethmac/trunk/rtl/verilog/
164	Ethernet debug registers removed.	mohor	8045d 08h	/ethmac/trunk/rtl/verilog/

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 250

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