URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 250

Rev	Log message	Author	Age	Path
211	Bist added.	mohor	7869d 01h	/ethmac/trunk/rtl/verilog/
210	BIST added.	mohor	7869d 01h	/ethmac/trunk/rtl/verilog/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7885d 23h	/ethmac/trunk/rtl/verilog/
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7885d 23h	/ethmac/trunk/rtl/verilog/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7889d 00h	/ethmac/trunk/rtl/verilog/
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7897d 03h	/ethmac/trunk/rtl/verilog/
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7898d 03h	/ethmac/trunk/rtl/verilog/
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7899d 04h	/ethmac/trunk/rtl/verilog/
165	HASH improvement needed.	mohor	7899d 07h	/ethmac/trunk/rtl/verilog/
164	Ethernet debug registers removed.	mohor	7899d 07h	/ethmac/trunk/rtl/verilog/