URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 275

Rev	Log message	Author	Age	Path
238	Defines fixed to use generic RAM by default.	mohor	7854d 05h	/ethmac/trunk/rtl/verilog/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7856d 10h	/ethmac/trunk/rtl/verilog/
232	fpga define added.	mohor	7862d 04h	/ethmac/trunk/rtl/verilog/
229	case changed to casex.	mohor	7868d 02h	/ethmac/trunk/rtl/verilog/
227	Changed BIST scan signals.	tadejm	7868d 06h	/ethmac/trunk/rtl/verilog/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7868d 07h	/ethmac/trunk/rtl/verilog/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7872d 07h	/ethmac/trunk/rtl/verilog/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7875d 07h	/ethmac/trunk/rtl/verilog/
218	Typo error fixed. (When using Bist)	mohor	7875d 09h	/ethmac/trunk/rtl/verilog/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7876d 06h	/ethmac/trunk/rtl/verilog/