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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 29

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29 Generic memory model is used. Defines are changed for the same reason. mohor 7537d 03h /ethmac/trunk/rtl/verilog/
24 Log file added. mohor 7562d 06h /ethmac/trunk/rtl/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 7562d 06h /ethmac/trunk/rtl/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7562d 09h /ethmac/trunk/rtl/verilog/
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 7563d 06h /ethmac/trunk/rtl/verilog/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 7587d 03h /ethmac/trunk/rtl/verilog/
18 Few little NCSIM warnings fixed. mohor 7600d 03h /ethmac/trunk/rtl/verilog/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 7627d 04h /ethmac/trunk/rtl/verilog/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 7634d 09h /ethmac/trunk/rtl/verilog/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7636d 03h /ethmac/trunk/rtl/verilog/
14 Unconnected signals are now connected. mohor 7640d 08h /ethmac/trunk/rtl/verilog/
10 Directory structure changed. Files checked and joind together. mohor 7642d 20h /ethmac/trunk/rtl/verilog/

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