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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 297

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Rev Log message Author Age Path
297 Artisan ram instance added. simons 7646d 10h /ethmac/trunk/rtl/verilog
288 This file was not part of the RTL before, but it should be here. simons 7682d 12h /ethmac/trunk/rtl/verilog
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 7708d 15h /ethmac/trunk/rtl/verilog
285 Binary operator used instead of unary (xnor). mohor 7708d 15h /ethmac/trunk/rtl/verilog
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7736d 17h /ethmac/trunk/rtl/verilog
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 7764d 10h /ethmac/trunk/rtl/verilog
280 Reset has priority in some flipflops. mohor 7842d 12h /ethmac/trunk/rtl/verilog
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7842d 13h /ethmac/trunk/rtl/verilog
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7842d 13h /ethmac/trunk/rtl/verilog
276 Defer indication changed. tadejm 7842d 13h /ethmac/trunk/rtl/verilog
275 Fix MTxErr or prevent sending too big frames. mohor 7849d 18h /ethmac/trunk/rtl/verilog
272 When control packets were received, they were ignored in some cases. tadejm 7850d 13h /ethmac/trunk/rtl/verilog
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7851d 15h /ethmac/trunk/rtl/verilog
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7852d 15h /ethmac/trunk/rtl/verilog
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7911d 13h /ethmac/trunk/rtl/verilog
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7912d 01h /ethmac/trunk/rtl/verilog
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 7913d 02h /ethmac/trunk/rtl/verilog
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 7913d 03h /ethmac/trunk/rtl/verilog
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 7913d 03h /ethmac/trunk/rtl/verilog
255 TPauseRq synchronized to tx_clk. mohor 7913d 03h /ethmac/trunk/rtl/verilog

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