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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 306

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Rev	Log message	Author	Age	Path
306	Lapsus fixed (!we -> ~we).	simons	7456d 15h	/ethmac/trunk/rtl/verilog/
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7478d 11h	/ethmac/trunk/rtl/verilog/
302	mbist signals updated according to newest convention	markom	7504d 22h	/ethmac/trunk/rtl/verilog/
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7515d 14h	/ethmac/trunk/rtl/verilog/
297	Artisan ram instance added.	simons	7568d 13h	/ethmac/trunk/rtl/verilog/
288	This file was not part of the RTL before, but it should be here.	simons	7604d 15h	/ethmac/trunk/rtl/verilog/
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7630d 18h	/ethmac/trunk/rtl/verilog/
285	Binary operator used instead of unary (xnor).	mohor	7630d 18h	/ethmac/trunk/rtl/verilog/
284	Busy was set 2 cycles too late. Reported by Dennis Scott.	mohor	7658d 19h	/ethmac/trunk/rtl/verilog/
283	RxBDAddress was updated also when value to r_TxBDNum was written with greater value than allowed.	mohor	7686d 13h	/ethmac/trunk/rtl/verilog/
280	Reset has priority in some flipflops.	mohor	7764d 15h	/ethmac/trunk/rtl/verilog/
278	A new bug (entered with previous update) fixed. When abort occured sometimes data transmission was blocked.	mohor	7764d 16h	/ethmac/trunk/rtl/verilog/
277	When padding was enabled and crc disabled, frame was not ended correctly.	mohor	7764d 16h	/ethmac/trunk/rtl/verilog/
276	Defer indication changed.	tadejm	7764d 16h	/ethmac/trunk/rtl/verilog/
275	Fix MTxErr or prevent sending too big frames.	mohor	7771d 20h	/ethmac/trunk/rtl/verilog/
272	When control packets were received, they were ignored in some cases.	tadejm	7772d 16h	/ethmac/trunk/rtl/verilog/
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7773d 17h	/ethmac/trunk/rtl/verilog/
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7774d 17h	/ethmac/trunk/rtl/verilog/
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	7833d 16h	/ethmac/trunk/rtl/verilog/
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7834d 04h	/ethmac/trunk/rtl/verilog/
259	In loopback rx_clk is not looped back. Possible CRC error. Consider if usage of additional logic is necessery (FIFO for looping the data).	mohor	7835d 05h	/ethmac/trunk/rtl/verilog/
257	When TxUsedData and CtrlMux occur at the same time, byte counter needs to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.	mohor	7835d 05h	/ethmac/trunk/rtl/verilog/
256	TxDone and TxAbort changed so they're not propagated to the wishbone module when control frame is transmitted.	mohor	7835d 05h	/ethmac/trunk/rtl/verilog/
255	TPauseRq synchronized to tx_clk.	mohor	7835d 05h	/ethmac/trunk/rtl/verilog/
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7836d 11h	/ethmac/trunk/rtl/verilog/
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	7836d 12h	/ethmac/trunk/rtl/verilog/
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7836d 12h	/ethmac/trunk/rtl/verilog/
248	wb_rst_i is used for MIIM reset.	mohor	7837d 12h	/ethmac/trunk/rtl/verilog/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7840d 15h	/ethmac/trunk/rtl/verilog/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7841d 11h	/ethmac/trunk/rtl/verilog/

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 306

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