URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 330

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
330	Warning fixes.	igorm	7015d 20h	/ethmac/trunk/rtl/verilog/
329	Defer indication fixed.	igorm	7015d 22h	/ethmac/trunk/rtl/verilog/
328	Delayed CRC fixed.	igorm	7015d 22h	/ethmac/trunk/rtl/verilog/
327	Defer indication fixed.	igorm	7015d 22h	/ethmac/trunk/rtl/verilog/
326	Delayed CRC fixed.	igorm	7015d 22h	/ethmac/trunk/rtl/verilog/
325	Defer indication fixed.	igorm	7015d 22h	/ethmac/trunk/rtl/verilog/
323	Accidently deleted line put back.	igorm	7312d 23h	/ethmac/trunk/rtl/verilog/
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7316d 18h	/ethmac/trunk/rtl/verilog/
320	TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.	igorm	7316d 21h	/ethmac/trunk/rtl/verilog/
317	Multicast detection fixed. Only the LSB of the first byte is checked.	igorm	7357d 00h	/ethmac/trunk/rtl/verilog/
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7459d 20h	/ethmac/trunk/rtl/verilog/
306	Lapsus fixed (!we -> ~we).	simons	7460d 18h	/ethmac/trunk/rtl/verilog/
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7482d 15h	/ethmac/trunk/rtl/verilog/
302	mbist signals updated according to newest convention	markom	7509d 01h	/ethmac/trunk/rtl/verilog/
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7519d 17h	/ethmac/trunk/rtl/verilog/
297	Artisan ram instance added.	simons	7572d 16h	/ethmac/trunk/rtl/verilog/
288	This file was not part of the RTL before, but it should be here.	simons	7608d 18h	/ethmac/trunk/rtl/verilog/
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7634d 21h	/ethmac/trunk/rtl/verilog/
285	Binary operator used instead of unary (xnor).	mohor	7634d 22h	/ethmac/trunk/rtl/verilog/
284	Busy was set 2 cycles too late. Reported by Dennis Scott.	mohor	7662d 23h	/ethmac/trunk/rtl/verilog/
283	RxBDAddress was updated also when value to r_TxBDNum was written with greater value than allowed.	mohor	7690d 17h	/ethmac/trunk/rtl/verilog/
280	Reset has priority in some flipflops.	mohor	7768d 18h	/ethmac/trunk/rtl/verilog/
278	A new bug (entered with previous update) fixed. When abort occured sometimes data transmission was blocked.	mohor	7768d 19h	/ethmac/trunk/rtl/verilog/
277	When padding was enabled and crc disabled, frame was not ended correctly.	mohor	7768d 20h	/ethmac/trunk/rtl/verilog/
276	Defer indication changed.	tadejm	7768d 20h	/ethmac/trunk/rtl/verilog/
275	Fix MTxErr or prevent sending too big frames.	mohor	7776d 00h	/ethmac/trunk/rtl/verilog/
272	When control packets were received, they were ignored in some cases.	tadejm	7776d 19h	/ethmac/trunk/rtl/verilog/
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7777d 21h	/ethmac/trunk/rtl/verilog/
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7778d 21h	/ethmac/trunk/rtl/verilog/
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	7837d 20h	/ethmac/trunk/rtl/verilog/

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 330

Filtering Options