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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 352

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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 3459d 04h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 3467d 18h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3467d 19h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 3468d 19h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 3469d 21h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3479d 21h /ethmac/trunk/rtl/verilog/
338 root 4273d 23h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 4331d 05h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 5779d 18h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 5793d 00h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 5808d 02h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 5808d 03h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 5808d 03h /ethmac/trunk/rtl/verilog/
327 Defer indication fixed. igorm 5808d 03h /ethmac/trunk/rtl/verilog/
326 Delayed CRC fixed. igorm 5808d 04h /ethmac/trunk/rtl/verilog/
325 Defer indication fixed. igorm 5808d 04h /ethmac/trunk/rtl/verilog/
323 Accidently deleted line put back. igorm 6105d 04h /ethmac/trunk/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 6108d 23h /ethmac/trunk/rtl/verilog/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 6109d 03h /ethmac/trunk/rtl/verilog/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 6149d 05h /ethmac/trunk/rtl/verilog/

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