URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 356

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Rev	Log message	Author	Age	Path
356	Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure	olof	4795d 04h	/ethmac/trunk/rtl/verilog/
355	Import Julius Baxter's verilator hints from ORPSoC	olof	4795d 05h	/ethmac/trunk/rtl/verilog/
354	Whitespace cleanup	olof	4795d 06h	/ethmac/trunk/rtl/verilog/
353	Inherit fixes for bit width of constants from ORPSoC	olof	4797d 07h	/ethmac/trunk/rtl/verilog/
352	Removed delayed assignments from rtl code	olof	4801d 13h	/ethmac/trunk/rtl/verilog/
351	Turn defines into parameters in eth_cop	olof	4810d 03h	/ethmac/trunk/rtl/verilog/
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	4810d 03h	/ethmac/trunk/rtl/verilog/
349	Make all parameters configurable from top level	olof	4811d 04h	/ethmac/trunk/rtl/verilog/
346	Updated project location	olof	4812d 06h	/ethmac/trunk/rtl/verilog/
341	Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short	olof	4822d 06h	/ethmac/trunk/rtl/verilog/
338		root	5616d 08h	/ethmac/trunk/rtl/verilog/
335	New directory structure.	root	5673d 13h	/ethmac/trunk/rtl/verilog/
333	Some small fixes + some troubles fixed.	igorm	7122d 03h	/ethmac/trunk/rtl/verilog/
332	Case statement improved for synthesys.	igorm	7135d 09h	/ethmac/trunk/rtl/verilog/
330	Warning fixes.	igorm	7150d 11h	/ethmac/trunk/rtl/verilog/
329	Defer indication fixed.	igorm	7150d 12h	/ethmac/trunk/rtl/verilog/
328	Delayed CRC fixed.	igorm	7150d 12h	/ethmac/trunk/rtl/verilog/
327	Defer indication fixed.	igorm	7150d 12h	/ethmac/trunk/rtl/verilog/
326	Delayed CRC fixed.	igorm	7150d 12h	/ethmac/trunk/rtl/verilog/
325	Defer indication fixed.	igorm	7150d 13h	/ethmac/trunk/rtl/verilog/

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 356

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