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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 357

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Rev Log message Author Age Path
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3989d 13h /ethmac/trunk/rtl/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3989d 15h /ethmac/trunk/rtl/verilog/
355 Import Julius Baxter's verilator hints from ORPSoC olof 3989d 16h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 3989d 16h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 3991d 17h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 3995d 23h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4004d 13h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4004d 14h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4005d 14h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4006d 16h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4016d 16h /ethmac/trunk/rtl/verilog/
338 root 4810d 18h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 4868d 00h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 6316d 14h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 6329d 19h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 6344d 21h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 6344d 22h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 6344d 22h /ethmac/trunk/rtl/verilog/
327 Defer indication fixed. igorm 6344d 23h /ethmac/trunk/rtl/verilog/
326 Delayed CRC fixed. igorm 6344d 23h /ethmac/trunk/rtl/verilog/

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