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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 358

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Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4649d 03h /ethmac/trunk/rtl/verilog/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4649d 03h /ethmac/trunk/rtl/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4649d 05h /ethmac/trunk/rtl/verilog/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4649d 06h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 4649d 06h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4651d 08h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4655d 13h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4664d 03h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4664d 04h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4665d 04h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4666d 06h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4676d 06h /ethmac/trunk/rtl/verilog/
338 root 5470d 09h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 5527d 14h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 6976d 04h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 6989d 09h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 7004d 11h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 7004d 12h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 7004d 12h /ethmac/trunk/rtl/verilog/
327 Defer indication fixed. igorm 7004d 13h /ethmac/trunk/rtl/verilog/
326 Delayed CRC fixed. igorm 7004d 13h /ethmac/trunk/rtl/verilog/
325 Defer indication fixed. igorm 7004d 13h /ethmac/trunk/rtl/verilog/
323 Accidently deleted line put back. igorm 7301d 13h /ethmac/trunk/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7305d 08h /ethmac/trunk/rtl/verilog/
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7305d 12h /ethmac/trunk/rtl/verilog/
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7345d 14h /ethmac/trunk/rtl/verilog/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7448d 11h /ethmac/trunk/rtl/verilog/
306 Lapsus fixed (!we -> ~we). simons 7449d 09h /ethmac/trunk/rtl/verilog/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7471d 05h /ethmac/trunk/rtl/verilog/
302 mbist signals updated according to newest convention markom 7497d 16h /ethmac/trunk/rtl/verilog/

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