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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 359

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Rev Log message Author Age Path
359 Verilator linting fixes olof 4657d 04h /ethmac/trunk/rtl/verilog
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4658d 18h /ethmac/trunk/rtl/verilog
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4658d 19h /ethmac/trunk/rtl/verilog
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4658d 20h /ethmac/trunk/rtl/verilog
355 Import Julius Baxter's verilator hints from ORPSoC olof 4658d 21h /ethmac/trunk/rtl/verilog
354 Whitespace cleanup olof 4658d 22h /ethmac/trunk/rtl/verilog
353 Inherit fixes for bit width of constants from ORPSoC olof 4660d 23h /ethmac/trunk/rtl/verilog
352 Removed delayed assignments from rtl code olof 4665d 05h /ethmac/trunk/rtl/verilog
351 Turn defines into parameters in eth_cop olof 4673d 19h /ethmac/trunk/rtl/verilog
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4673d 19h /ethmac/trunk/rtl/verilog
349 Make all parameters configurable from top level olof 4674d 20h /ethmac/trunk/rtl/verilog
346 Updated project location olof 4675d 22h /ethmac/trunk/rtl/verilog
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4685d 22h /ethmac/trunk/rtl/verilog
338 root 5480d 00h /ethmac/trunk/rtl/verilog
335 New directory structure. root 5537d 05h /ethmac/trunk/rtl/verilog
333 Some small fixes + some troubles fixed. igorm 6985d 19h /ethmac/trunk/rtl/verilog
332 Case statement improved for synthesys. igorm 6999d 01h /ethmac/trunk/rtl/verilog
330 Warning fixes. igorm 7014d 03h /ethmac/trunk/rtl/verilog
329 Defer indication fixed. igorm 7014d 04h /ethmac/trunk/rtl/verilog
328 Delayed CRC fixed. igorm 7014d 04h /ethmac/trunk/rtl/verilog

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