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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 364

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Rev Log message Author Age Path
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4701d 01h /ethmac/trunk/rtl/verilog/
360 Added partial implementation of the debug register from ORPSoC olof 4702d 09h /ethmac/trunk/rtl/verilog/
359 Verilator linting fixes olof 4704d 11h /ethmac/trunk/rtl/verilog/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4706d 01h /ethmac/trunk/rtl/verilog/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4706d 01h /ethmac/trunk/rtl/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4706d 03h /ethmac/trunk/rtl/verilog/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4706d 04h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 4706d 04h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4708d 06h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4712d 12h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4721d 01h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4721d 02h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4722d 03h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4723d 04h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4733d 04h /ethmac/trunk/rtl/verilog/
338 root 5527d 07h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 5584d 12h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 7033d 02h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 7046d 07h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 7061d 09h /ethmac/trunk/rtl/verilog/

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