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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 367

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Rev Log message Author Age Path
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 3891d 15h /ethmac/trunk/rtl/verilog/
366 Readded eth_top.v with a deprecation warning olof 4015d 19h /ethmac/trunk/rtl/verilog/
365 Whitespace cleanup olof 4016d 18h /ethmac/trunk/rtl/verilog/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4017d 16h /ethmac/trunk/rtl/verilog/
360 Added partial implementation of the debug register from ORPSoC olof 4019d 00h /ethmac/trunk/rtl/verilog/
359 Verilator linting fixes olof 4021d 02h /ethmac/trunk/rtl/verilog/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4022d 16h /ethmac/trunk/rtl/verilog/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4022d 16h /ethmac/trunk/rtl/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4022d 18h /ethmac/trunk/rtl/verilog/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4022d 19h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 4022d 19h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4024d 20h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4029d 02h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4037d 16h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4037d 17h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4038d 17h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4039d 19h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4049d 19h /ethmac/trunk/rtl/verilog/
338 root 4843d 21h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 4901d 03h /ethmac/trunk/rtl/verilog/

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