OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 367

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 4525d 18h /ethmac/trunk/rtl/verilog
366 Readded eth_top.v with a deprecation warning olof 4649d 22h /ethmac/trunk/rtl/verilog
365 Whitespace cleanup olof 4650d 22h /ethmac/trunk/rtl/verilog
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4651d 19h /ethmac/trunk/rtl/verilog
360 Added partial implementation of the debug register from ORPSoC olof 4653d 03h /ethmac/trunk/rtl/verilog
359 Verilator linting fixes olof 4655d 05h /ethmac/trunk/rtl/verilog
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4656d 19h /ethmac/trunk/rtl/verilog
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4656d 19h /ethmac/trunk/rtl/verilog
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4656d 21h /ethmac/trunk/rtl/verilog
355 Import Julius Baxter's verilator hints from ORPSoC olof 4656d 22h /ethmac/trunk/rtl/verilog
354 Whitespace cleanup olof 4656d 22h /ethmac/trunk/rtl/verilog
353 Inherit fixes for bit width of constants from ORPSoC olof 4659d 00h /ethmac/trunk/rtl/verilog
352 Removed delayed assignments from rtl code olof 4663d 06h /ethmac/trunk/rtl/verilog
351 Turn defines into parameters in eth_cop olof 4671d 19h /ethmac/trunk/rtl/verilog
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4671d 20h /ethmac/trunk/rtl/verilog
349 Make all parameters configurable from top level olof 4672d 21h /ethmac/trunk/rtl/verilog
346 Updated project location olof 4673d 22h /ethmac/trunk/rtl/verilog
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4683d 22h /ethmac/trunk/rtl/verilog
338 root 5478d 01h /ethmac/trunk/rtl/verilog
335 New directory structure. root 5535d 06h /ethmac/trunk/rtl/verilog

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.