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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 46

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Rev Log message Author Age Path
46 HASH0 and HASH1 registers added. mohor 8139d 07h /ethmac/trunk/rtl/verilog/
43 Tx status is written back to the BD. mohor 8140d 15h /ethmac/trunk/rtl/verilog/
42 Rx status is written back to the BD. mohor 8143d 08h /ethmac/trunk/rtl/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8145d 10h /ethmac/trunk/rtl/verilog/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 8146d 07h /ethmac/trunk/rtl/verilog/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.
mohor 8150d 11h /ethmac/trunk/rtl/verilog/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8159d 13h /ethmac/trunk/rtl/verilog/
37 Link in the header changed. mohor 8159d 13h /ethmac/trunk/rtl/verilog/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8208d 09h /ethmac/trunk/rtl/verilog/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8208d 13h /ethmac/trunk/rtl/verilog/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8208d 14h /ethmac/trunk/rtl/verilog/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8230d 10h /ethmac/trunk/rtl/verilog/
24 Log file added. mohor 8255d 12h /ethmac/trunk/rtl/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 8255d 12h /ethmac/trunk/rtl/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8255d 15h /ethmac/trunk/rtl/verilog/
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 8256d 12h /ethmac/trunk/rtl/verilog/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8280d 09h /ethmac/trunk/rtl/verilog/
18 Few little NCSIM warnings fixed. mohor 8293d 10h /ethmac/trunk/rtl/verilog/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8320d 10h /ethmac/trunk/rtl/verilog/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8327d 15h /ethmac/trunk/rtl/verilog/

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