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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 52

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Rev Log message Author Age Path
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 7651d 17h /ethmac/trunk/rtl/verilog/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 7651d 18h /ethmac/trunk/rtl/verilog/
48 RxOverRun added to statuses. mohor 7653d 20h /ethmac/trunk/rtl/verilog/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.
mohor 7653d 20h /ethmac/trunk/rtl/verilog/
46 HASH0 and HASH1 registers added. mohor 7653d 20h /ethmac/trunk/rtl/verilog/
43 Tx status is written back to the BD. mohor 7655d 04h /ethmac/trunk/rtl/verilog/
42 Rx status is written back to the BD. mohor 7657d 21h /ethmac/trunk/rtl/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 7659d 23h /ethmac/trunk/rtl/verilog/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 7660d 20h /ethmac/trunk/rtl/verilog/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.
mohor 7665d 00h /ethmac/trunk/rtl/verilog/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 7674d 02h /ethmac/trunk/rtl/verilog/
37 Link in the header changed. mohor 7674d 03h /ethmac/trunk/rtl/verilog/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 7722d 22h /ethmac/trunk/rtl/verilog/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 7723d 02h /ethmac/trunk/rtl/verilog/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 7723d 03h /ethmac/trunk/rtl/verilog/
29 Generic memory model is used. Defines are changed for the same reason. mohor 7744d 23h /ethmac/trunk/rtl/verilog/
24 Log file added. mohor 7770d 02h /ethmac/trunk/rtl/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 7770d 02h /ethmac/trunk/rtl/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7770d 04h /ethmac/trunk/rtl/verilog/
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 7771d 01h /ethmac/trunk/rtl/verilog/

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