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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 52

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20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8308d 19h /ethmac/trunk/rtl/verilog
18 Few little NCSIM warnings fixed. mohor 8321d 20h /ethmac/trunk/rtl/verilog
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8348d 20h /ethmac/trunk/rtl/verilog
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8356d 02h /ethmac/trunk/rtl/verilog
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8357d 19h /ethmac/trunk/rtl/verilog
14 Unconnected signals are now connected. mohor 8362d 01h /ethmac/trunk/rtl/verilog
10 Directory structure changed. Files checked and joind together. mohor 8364d 13h /ethmac/trunk/rtl/verilog

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