URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 53

Rev	Log message	Author	Age	Path
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8230d 02h	/ethmac/trunk/rtl/verilog/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8253d 23h	/ethmac/trunk/rtl/verilog/
18	Few little NCSIM warnings fixed.	mohor	8267d 00h	/ethmac/trunk/rtl/verilog/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8294d 00h	/ethmac/trunk/rtl/verilog/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8301d 06h	/ethmac/trunk/rtl/verilog/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8302d 23h	/ethmac/trunk/rtl/verilog/
14	Unconnected signals are now connected.	mohor	8307d 05h	/ethmac/trunk/rtl/verilog/
10	Directory structure changed. Files checked and joind together.	mohor	8309d 17h	/ethmac/trunk/rtl/verilog/