URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 58

Rev	Log message	Author	Age	Path
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8193d 11h	/ethmac/trunk/rtl/verilog
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8215d 06h	/ethmac/trunk/rtl/verilog
24	Log file added.	mohor	8240d 09h	/ethmac/trunk/rtl/verilog
23	Number of addresses (wb_adr_i) minimized.	mohor	8240d 09h	/ethmac/trunk/rtl/verilog
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8240d 12h	/ethmac/trunk/rtl/verilog
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8241d 09h	/ethmac/trunk/rtl/verilog
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8265d 06h	/ethmac/trunk/rtl/verilog
18	Few little NCSIM warnings fixed.	mohor	8278d 07h	/ethmac/trunk/rtl/verilog
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8305d 07h	/ethmac/trunk/rtl/verilog
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8312d 12h	/ethmac/trunk/rtl/verilog