OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 64

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 8287d 22h /ethmac/trunk/rtl/verilog/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.
mohor 8292d 02h /ethmac/trunk/rtl/verilog/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8301d 04h /ethmac/trunk/rtl/verilog/
37 Link in the header changed. mohor 8301d 04h /ethmac/trunk/rtl/verilog/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8350d 00h /ethmac/trunk/rtl/verilog/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8350d 04h /ethmac/trunk/rtl/verilog/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8350d 05h /ethmac/trunk/rtl/verilog/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8372d 00h /ethmac/trunk/rtl/verilog/
24 Log file added. mohor 8397d 03h /ethmac/trunk/rtl/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 8397d 03h /ethmac/trunk/rtl/verilog/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.