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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 64

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Rev Log message Author Age Path
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8119d 11h /ethmac/trunk/rtl/verilog
63 RxAbort is connected differently. mohor 8119d 14h /ethmac/trunk/rtl/verilog
62 RxAbort is an output. No need to have is declared as wire. mohor 8119d 14h /ethmac/trunk/rtl/verilog
61 RxStartFrm cleared when abort or retry comes. mohor 8119d 16h /ethmac/trunk/rtl/verilog
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8119d 16h /ethmac/trunk/rtl/verilog
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8119d 16h /ethmac/trunk/rtl/verilog
58 File format changed. mohor 8119d 17h /ethmac/trunk/rtl/verilog
57 Format of the file changed a bit. mohor 8119d 17h /ethmac/trunk/rtl/verilog
56 File format fixed a bit. mohor 8119d 17h /ethmac/trunk/rtl/verilog
55 Changed that were lost with last update put back to the file. mohor 8119d 17h /ethmac/trunk/rtl/verilog
54 Addition of new module eth_addrcheck.v billditt 8120d 07h /ethmac/trunk/rtl/verilog
53 Addition of new module eth_addrcheck.v billditt 8120d 07h /ethmac/trunk/rtl/verilog
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8120d 08h /ethmac/trunk/rtl/verilog
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 8120d 09h /ethmac/trunk/rtl/verilog
48 RxOverRun added to statuses. mohor 8122d 11h /ethmac/trunk/rtl/verilog
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8122d 11h /ethmac/trunk/rtl/verilog
46 HASH0 and HASH1 registers added. mohor 8122d 11h /ethmac/trunk/rtl/verilog
43 Tx status is written back to the BD. mohor 8123d 19h /ethmac/trunk/rtl/verilog
42 Rx status is written back to the BD. mohor 8126d 12h /ethmac/trunk/rtl/verilog
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8128d 14h /ethmac/trunk/rtl/verilog

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