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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 69


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Rev Log message Author Age Path
69 Define missmatch fixed. mohor 7480d 22h /ethmac/trunk/rtl/verilog/
68 Registered trimmed. Unused registers removed. mohor 7481d 21h /ethmac/trunk/rtl/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 7481d 22h /ethmac/trunk/rtl/verilog/
65 Testbench fixed, code simplified, unused signals removed. mohor 7482d 04h /ethmac/trunk/rtl/verilog/
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 7482d 18h /ethmac/trunk/rtl/verilog/
63 RxAbort is connected differently. mohor 7482d 21h /ethmac/trunk/rtl/verilog/
62 RxAbort is an output. No need to have is declared as wire. mohor 7482d 22h /ethmac/trunk/rtl/verilog/
61 RxStartFrm cleared when abort or retry comes. mohor 7482d 23h /ethmac/trunk/rtl/verilog/
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 7482d 23h /ethmac/trunk/rtl/verilog/
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 7483d 00h /ethmac/trunk/rtl/verilog/
58 File format changed. mohor 7483d 00h /ethmac/trunk/rtl/verilog/
57 Format of the file changed a bit. mohor 7483d 00h /ethmac/trunk/rtl/verilog/
56 File format fixed a bit. mohor 7483d 00h /ethmac/trunk/rtl/verilog/
55 Changed that were lost with last update put back to the file. mohor 7483d 00h /ethmac/trunk/rtl/verilog/
54 Addition of new module eth_addrcheck.v billditt 7483d 14h /ethmac/trunk/rtl/verilog/
53 Addition of new module eth_addrcheck.v billditt 7483d 14h /ethmac/trunk/rtl/verilog/
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 7483d 15h /ethmac/trunk/rtl/verilog/
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 7483d 16h /ethmac/trunk/rtl/verilog/
48 RxOverRun added to statuses. mohor 7485d 18h /ethmac/trunk/rtl/verilog/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.
mohor 7485d 18h /ethmac/trunk/rtl/verilog/

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