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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 70

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Rev Log message Author Age Path
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.
mohor 8255d 12h /ethmac/trunk/rtl/verilog/
46 HASH0 and HASH1 registers added. mohor 8255d 12h /ethmac/trunk/rtl/verilog/
43 Tx status is written back to the BD. mohor 8256d 20h /ethmac/trunk/rtl/verilog/
42 Rx status is written back to the BD. mohor 8259d 13h /ethmac/trunk/rtl/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8261d 15h /ethmac/trunk/rtl/verilog/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 8262d 12h /ethmac/trunk/rtl/verilog/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.
mohor 8266d 16h /ethmac/trunk/rtl/verilog/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8275d 18h /ethmac/trunk/rtl/verilog/
37 Link in the header changed. mohor 8275d 19h /ethmac/trunk/rtl/verilog/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8324d 14h /ethmac/trunk/rtl/verilog/

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