URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 72

Rev	Log message	Author	Age	Path
48	RxOverRun added to statuses.	mohor	8125d 19h	/ethmac/trunk/rtl/verilog
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8125d 19h	/ethmac/trunk/rtl/verilog
46	HASH0 and HASH1 registers added.	mohor	8125d 19h	/ethmac/trunk/rtl/verilog
43	Tx status is written back to the BD.	mohor	8127d 03h	/ethmac/trunk/rtl/verilog
42	Rx status is written back to the BD.	mohor	8129d 20h	/ethmac/trunk/rtl/verilog
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8131d 22h	/ethmac/trunk/rtl/verilog
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8132d 19h	/ethmac/trunk/rtl/verilog
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8136d 23h	/ethmac/trunk/rtl/verilog
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8146d 01h	/ethmac/trunk/rtl/verilog
37	Link in the header changed.	mohor	8146d 02h	/ethmac/trunk/rtl/verilog