OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 96

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8119d 14h /ethmac/trunk/rtl/verilog/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 8119d 17h /ethmac/trunk/rtl/verilog/
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 8119d 17h /ethmac/trunk/rtl/verilog/
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8124d 15h /ethmac/trunk/rtl/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 8125d 17h /ethmac/trunk/rtl/verilog/
91 Comments in Slovene language removed. mohor 8125d 17h /ethmac/trunk/rtl/verilog/
90 casex changed with case, fifo reset changed. mohor 8125d 17h /ethmac/trunk/rtl/verilog/
88 rx_fifo was not always cleared ok. Fixed. mohor 8135d 14h /ethmac/trunk/rtl/verilog/
87 Status was not latched correctly sometimes. Fixed. mohor 8135d 16h /ethmac/trunk/rtl/verilog/
86 Big Endian problem when sending frames fixed. mohor 8136d 23h /ethmac/trunk/rtl/verilog/
85 Log info was missing. mohor 8142d 09h /ethmac/trunk/rtl/verilog/
84 LinkFail signal was not latching appropriate bit. mohor 8142d 09h /ethmac/trunk/rtl/verilog/
83 MAC address recognition was not correct (bytes swaped). mohor 8142d 09h /ethmac/trunk/rtl/verilog/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8142d 11h /ethmac/trunk/rtl/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8146d 13h /ethmac/trunk/rtl/verilog/
79 RetryCntLatched was unused and removed from design mohor 8146d 14h /ethmac/trunk/rtl/verilog/
78 WB_SEL_I was unused and removed from design mohor 8146d 14h /ethmac/trunk/rtl/verilog/
77 Interrupts changed mohor 8146d 14h /ethmac/trunk/rtl/verilog/
76 Interrupts changed in the top file mohor 8146d 14h /ethmac/trunk/rtl/verilog/
75 r_Bro is used for accepting/denying frames mohor 8146d 14h /ethmac/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.