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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 96

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Rev	Log message	Author	Age	Path
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8076d 03h	/ethmac/trunk/rtl/verilog/
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8076d 06h	/ethmac/trunk/rtl/verilog/
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8076d 06h	/ethmac/trunk/rtl/verilog/
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8081d 04h	/ethmac/trunk/rtl/verilog/
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8082d 06h	/ethmac/trunk/rtl/verilog/
91	Comments in Slovene language removed.	mohor	8082d 06h	/ethmac/trunk/rtl/verilog/
90	casex changed with case, fifo reset changed.	mohor	8082d 07h	/ethmac/trunk/rtl/verilog/
88	rx_fifo was not always cleared ok. Fixed.	mohor	8092d 03h	/ethmac/trunk/rtl/verilog/
87	Status was not latched correctly sometimes. Fixed.	mohor	8092d 06h	/ethmac/trunk/rtl/verilog/
86	Big Endian problem when sending frames fixed.	mohor	8093d 12h	/ethmac/trunk/rtl/verilog/
85	Log info was missing.	mohor	8098d 22h	/ethmac/trunk/rtl/verilog/
84	LinkFail signal was not latching appropriate bit.	mohor	8098d 22h	/ethmac/trunk/rtl/verilog/
83	MAC address recognition was not correct (bytes swaped).	mohor	8098d 22h	/ethmac/trunk/rtl/verilog/
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8099d 00h	/ethmac/trunk/rtl/verilog/
80	Small fixes for external/internal DMA missmatches.	mohor	8103d 02h	/ethmac/trunk/rtl/verilog/
79	RetryCntLatched was unused and removed from design	mohor	8103d 03h	/ethmac/trunk/rtl/verilog/
78	WB_SEL_I was unused and removed from design	mohor	8103d 03h	/ethmac/trunk/rtl/verilog/
77	Interrupts changed	mohor	8103d 03h	/ethmac/trunk/rtl/verilog/
76	Interrupts changed in the top file	mohor	8103d 03h	/ethmac/trunk/rtl/verilog/
75	r_Bro is used for accepting/denying frames	mohor	8103d 03h	/ethmac/trunk/rtl/verilog/
74	Reset values are passed to registers through parameters	mohor	8103d 03h	/ethmac/trunk/rtl/verilog/
73	Number of interrupts changed	mohor	8103d 03h	/ethmac/trunk/rtl/verilog/
72	Retry is not activated when a Tx Underrun occured	mohor	8107d 06h	/ethmac/trunk/rtl/verilog/
70	Small fixes.	mohor	8111d 09h	/ethmac/trunk/rtl/verilog/
69	Define missmatch fixed.	mohor	8112d 06h	/ethmac/trunk/rtl/verilog/
68	Registered trimmed. Unused registers removed.	mohor	8113d 05h	/ethmac/trunk/rtl/verilog/
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8113d 06h	/ethmac/trunk/rtl/verilog/
65	Testbench fixed, code simplified, unused signals removed.	mohor	8113d 12h	/ethmac/trunk/rtl/verilog/
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8114d 02h	/ethmac/trunk/rtl/verilog/
63	RxAbort is connected differently.	mohor	8114d 06h	/ethmac/trunk/rtl/verilog/

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 96

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