OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 346

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
346 Updated project location olof 4929d 18h /ethmac/trunk/rtl/verilog/eth_macstatus.v
338 root 5733d 21h /ethmac/trunk/rtl/verilog/eth_macstatus.v
335 New directory structure. root 5791d 02h /ethmac/trunk/rtl/verilog/eth_macstatus.v
333 Some small fixes + some troubles fixed. igorm 7239d 16h /ethmac/trunk/rtl/verilog/eth_macstatus.v
325 Defer indication fixed. igorm 7268d 01h /ethmac/trunk/rtl/verilog/eth_macstatus.v
276 Defer indication changed. tadejm 8020d 22h /ethmac/trunk/rtl/verilog/eth_macstatus.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 8090d 10h /ethmac/trunk/rtl/verilog/eth_macstatus.v
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 8098d 13h /ethmac/trunk/rtl/verilog/eth_macstatus.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 8160d 21h /ethmac/trunk/rtl/verilog/eth_macstatus.v
146 CarrierSenseLost status is not set when working in loopback mode. mohor 8168d 17h /ethmac/trunk/rtl/verilog/eth_macstatus.v
126 InvalidSymbol generation changed. mohor 8209d 18h /ethmac/trunk/rtl/verilog/eth_macstatus.v
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8303d 22h /ethmac/trunk/rtl/verilog/eth_macstatus.v
70 Small fixes. mohor 8367d 01h /ethmac/trunk/rtl/verilog/eth_macstatus.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8369d 19h /ethmac/trunk/rtl/verilog/eth_macstatus.v
43 Tx status is written back to the BD. mohor 8374d 03h /ethmac/trunk/rtl/verilog/eth_macstatus.v
42 Rx status is written back to the BD. mohor 8376d 20h /ethmac/trunk/rtl/verilog/eth_macstatus.v
37 Link in the header changed. mohor 8393d 01h /ethmac/trunk/rtl/verilog/eth_macstatus.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8489d 03h /ethmac/trunk/rtl/verilog/eth_macstatus.v
18 Few little NCSIM warnings fixed. mohor 8526d 22h /ethmac/trunk/rtl/verilog/eth_macstatus.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8562d 21h /ethmac/trunk/rtl/verilog/eth_macstatus.v

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.