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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 354

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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 4029d 10h /ethmac/trunk/rtl/verilog/eth_macstatus.v
346 Updated project location olof 4040d 03h /ethmac/trunk/rtl/verilog/eth_macstatus.v
338 root 4844d 05h /ethmac/trunk/rtl/verilog/eth_macstatus.v
335 New directory structure. root 4901d 10h /ethmac/trunk/rtl/verilog/eth_macstatus.v
333 Some small fixes + some troubles fixed. igorm 6350d 00h /ethmac/trunk/rtl/verilog/eth_macstatus.v
325 Defer indication fixed. igorm 6378d 10h /ethmac/trunk/rtl/verilog/eth_macstatus.v
276 Defer indication changed. tadejm 7131d 07h /ethmac/trunk/rtl/verilog/eth_macstatus.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7200d 19h /ethmac/trunk/rtl/verilog/eth_macstatus.v
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7208d 22h /ethmac/trunk/rtl/verilog/eth_macstatus.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7271d 06h /ethmac/trunk/rtl/verilog/eth_macstatus.v
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7279d 02h /ethmac/trunk/rtl/verilog/eth_macstatus.v
126 InvalidSymbol generation changed. mohor 7320d 02h /ethmac/trunk/rtl/verilog/eth_macstatus.v
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7414d 07h /ethmac/trunk/rtl/verilog/eth_macstatus.v
70 Small fixes. mohor 7477d 10h /ethmac/trunk/rtl/verilog/eth_macstatus.v
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 7480d 03h /ethmac/trunk/rtl/verilog/eth_macstatus.v
43 Tx status is written back to the BD. mohor 7484d 11h /ethmac/trunk/rtl/verilog/eth_macstatus.v
42 Rx status is written back to the BD. mohor 7487d 04h /ethmac/trunk/rtl/verilog/eth_macstatus.v
37 Link in the header changed. mohor 7503d 10h /ethmac/trunk/rtl/verilog/eth_macstatus.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7599d 12h /ethmac/trunk/rtl/verilog/eth_macstatus.v
18 Few little NCSIM warnings fixed. mohor 7637d 06h /ethmac/trunk/rtl/verilog/eth_macstatus.v

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