Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_miim.v] - Rev 354


Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
354 Whitespace cleanup olof 4323d 22h /ethmac/trunk/rtl/verilog/eth_miim.v
352 Removed delayed assignments from rtl code olof 4330d 05h /ethmac/trunk/rtl/verilog/eth_miim.v
349 Make all parameters configurable from top level olof 4339d 20h /ethmac/trunk/rtl/verilog/eth_miim.v
346 Updated project location olof 4340d 22h /ethmac/trunk/rtl/verilog/eth_miim.v
338 root 5145d 00h /ethmac/trunk/rtl/verilog/eth_miim.v
335 New directory structure. root 5202d 05h /ethmac/trunk/rtl/verilog/eth_miim.v
333 Some small fixes + some troubles fixed. igorm 6650d 19h /ethmac/trunk/rtl/verilog/eth_miim.v
330 Warning fixes. igorm 6679d 03h /ethmac/trunk/rtl/verilog/eth_miim.v
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7326d 05h /ethmac/trunk/rtl/verilog/eth_miim.v
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 7600d 21h /ethmac/trunk/rtl/verilog/eth_miim.v
37 Link in the header changed. mohor 7804d 05h /ethmac/trunk/rtl/verilog/eth_miim.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7900d 07h /ethmac/trunk/rtl/verilog/eth_miim.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7974d 01h /ethmac/trunk/rtl/verilog/eth_miim.v

powered by: WebSVN 2.1.0

© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.