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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Rev 261

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Rev Log message Author Age Path
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7167d 05h /ethmac/trunk/rtl/verilog/eth_registers.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7169d 13h /ethmac/trunk/rtl/verilog/eth_registers.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7174d 12h /ethmac/trunk/rtl/verilog/eth_registers.v
164 Ethernet debug registers removed. mohor 7239d 20h /ethmac/trunk/rtl/verilog/eth_registers.v
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 7245d 12h /ethmac/trunk/rtl/verilog/eth_registers.v
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 7261d 15h /ethmac/trunk/rtl/verilog/eth_registers.v
141 Syntax error fixed. mohor 7264d 09h /ethmac/trunk/rtl/verilog/eth_registers.v
140 Syntax error fixed. mohor 7264d 09h /ethmac/trunk/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7264d 09h /ethmac/trunk/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7266d 13h /ethmac/trunk/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7380d 17h /ethmac/trunk/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 7435d 15h /ethmac/trunk/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 7444d 18h /ethmac/trunk/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 7445d 17h /ethmac/trunk/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 7446d 20h /ethmac/trunk/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 7447d 11h /ethmac/trunk/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 7449d 14h /ethmac/trunk/rtl/verilog/eth_registers.v
37 Link in the header changed. mohor 7469d 21h /ethmac/trunk/rtl/verilog/eth_registers.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 7518d 16h /ethmac/trunk/rtl/verilog/eth_registers.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 7518d 21h /ethmac/trunk/rtl/verilog/eth_registers.v

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